1. Field of Invention
This invention relates to a line computer, such as one used for controlling a manufacturing line control system; and more particularly, to an improvement in a function of a central processing unit installed in the line computer.
2. Description of the Prior Art
A manufacturing line control system which uses line computers is disclosed in applicant's U.S. Pat. No. 4,870,590. The line computer described in the patent is described herein as prior art.
First, the configuration of peripheral circuits around a CPU (central processing unit) board of the line computer is described with reference to FIG. 1, which shows the main parts of the conventional line computer system, wherein a high speed CPU, such as 68020 or 68030 which operates at 25 MHz clock or 33 MHz clock, is used, together with input/output (I/O) devices which operate at low speeds.
In FIG. 1, CPU 1 is connected to a main memory block 2 and low speed I/O devices 31,32 through data bus DB, address bus AB and other signal lines. Address signal ADR, read/write signal R/W, address strobe signal AS, and data strobe signal DS are inputted to a decoder 4 from CPU 1. From decoder 4, chip select signals CS1 and CS2 are outputted to I/O devices 31, 32. Further, data strobe acknowledge signals DSACK, DSACK1, and DSACK2 are transmitted to a single signal line from respective blocks 1, 2, 31, 32 every time these blocks transmit or receive the data.
FIG. 2 is a time chart showing in a plurality of lines the operation of the foregoing system. Assuming that CPU 1 has started a read cycle for I/O device 31, address ADR, address strobe signal AS(L), and data strobe signal DS(L) are transmitted from CPU 1. Decoder 4 interprets these signals and then sends chip select signal CS1(L) to I/O device 31. In response, I/O device 31 transmits read data (i.e., data read from I/O devices) corresponding to address ADR, to data bus DB. CPU 1 introduces this read data in accordance with information contained in the data strobe acknowledge signal .sup.DSACK1 (L). The read cycle ends with this operation.
Next, assuming that CPU 1 has started a write cycle for I/O device 32, address strobe signal AS(L) is transmitted from CPU 1. A bit later, data strobe signal DS(L) is transmitted. Decoder 4 interprets and then sends chip select signal CS2(L) to I/O device 32.
CPU 1 transmits write data to data bus DB. After introducing this write data, I/O device 32 functions to change data strobe acknowledge signal DSACK2 to an "L" state. The write cycle ends with this operation.
The FIG. 1 system repeats the read and write cycles.
The conventional system has various problems, among which are the following.
1. The address strobe signal AS(L) is asserted immediately after the cycle starts, and is negated immediately before the cycle ends. Thus, both set time t1 and hold time t2 of the address ADR are too short for the low speed I/O devices to operate reliably. Accordingly, the processing time for the low speed I/O devices is insufficient.
2. The last data strobe acknowledge signal DSACK1 does not change high impedance of the bus and the next data strobe acknowledge signal DSACK2 becomes an active (L). Accordingly, during time period t3 (see FIG. 2), an overlap of signals occurs on the same line.
3. Occasionally, the write cycle is executed immediately after the read cycle. In this case, if the write data were sent to data bus DB from CPU 1 when the last time read data exists in the same data bus, an overlap would occur between these two data during time period t4 (see FIG. 2).
4. Since data strobe signal DS(L) is cancelled immediately before the end of the write cycle, hold time t5 for the write data is insufficient for the low speed I/O device.
Accordingly, conventional systems leave room for improvement.